-- test_Y.vhd -- created mar. févr. 21 14:26:03 CET 2012 by whygee@f-cpu.org -- version mar. mars 20 17:57:34 CET 2012 : reboot Library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.yasep_definitions.all; use work.yasep_utils.all; entity test_uY is port( NUMERO: SLV4 := "0000" ); end test_uY; architecture toplevel of test_uY is signal WR_en : std_logic := '0'; signal WB_en : std_logic := '0'; signal phase : std_logic := '0'; signal ProgRdEn : std_logic := '1'; signal clk : std_logic := '0'; signal reset : std_logic := '0'; signal CARRY : std_logic := '0'; signal FlagZero : std_logic := '0'; signal condR1 : integer := 45; signal condition : std_logic := '0'; signal Condition2 : std_logic := '0'; signal Field_cond, Field_SI4, Field_SND : SLV4 := "0000"; signal PC : SLVAI := (SLVAI'range => '0'); signal NPC : SLVAI := (SLVAI'range => '0'); signal RAM_out : SLV16 := (SLV16'range => '0'); signal DST : SLV4 := "0000"; signal GetReadPort, PutWritePort, SRaddress: SLVY := (SLVY'range => '0'); signal GET_en : std_logic := '0'; signal PUT_en : std_logic := '0'; signal INV : std_logic := '0'; signal flag_addr : SLV4 := "0000"; signal flags_in : std_logic := '0'; signal flag_counter : integer := 20; signal A1_en : std_logic := '0'; signal R1, R2, R3, R4, R5, D1, D5, Result: SLVY := (SLVY'range => '0'); type PolyArrayType is array(0 to 15) of SLV16; signal PolyArray : PolyArrayType := ( std_logic_vector(to_unsigned(16#FFED#,16)), std_logic_vector(to_unsigned(16#FFEB#,16)), std_logic_vector(to_unsigned(16#FFA5#,16)), std_logic_vector(to_unsigned(16#FF71#,16)), std_logic_vector(to_unsigned(16#FF39#,16)), std_logic_vector(to_unsigned(16#FF35#,16)), std_logic_vector(to_unsigned(16#FF33#,16)), std_logic_vector(to_unsigned(16#FF05#,16)), std_logic_vector(to_unsigned(16#FEE9#,16)), std_logic_vector(to_unsigned(16#FE83#,16)), std_logic_vector(to_unsigned(16#FE49#,16)), std_logic_vector(to_unsigned(16#FE31#,16)), std_logic_vector(to_unsigned(16#FE25#,16)), std_logic_vector(to_unsigned(16#FDBF#,16)), std_logic_vector(to_unsigned(16#FDB3#,16)), std_logic_vector(to_unsigned(16#FD9B#,16))); begin ProgRAM: entity work.SynchRam16 port map( clk => clk, reset => reset, en => ProgRdEn, NPC => NPC, RAM_out => RAM_out); uY: entity work.microYASEP port map( ExecPrediv => "0010", NPC => NPC, PC => PC, RAM_out => RAM_out, ProgRdEn=>ProgRdEn, DST => DST, phase => phase, WB_en => WB_en, WR_en => WR_en, Carry => CARRY, FlagZero => FlagZero, Condition2 => Condition2, Condition => Condition, -- condR1 => condR1, Field_cond => Field_cond, Field_SI4 => Field_SI4, Field_SND => Field_SND, R1 => R1, R2 => R2, R3 => R3, R4 => R4, R5 => R5, D5 => D5, INV => INV, GetReadPort => GetReadPort, PutWritePort => PutWritePort, SRaddress => SRaddress, GET_en => GET_en, PUT_en => PUT_en, flag_addr => flag_addr, flags_in => flags_in, A1_en => A1_en, D1 => D1, Result => Result, clk => clk, reset => reset); observe: process(clk) variable i, j: integer; begin if clk='0' then -- and phase='1' then report " phase=" & std_logic'image(phase) & " WR_en=" & std_logic'image(WR_en) & " CARRY=" & std_logic'image(CARRY) & " Rd=" & std_logic'image(ProgRdEn) -- & " EQ=" & std_logic'image(FlagZero) -- & " cond=" & std_logic'image(condition) -- & " cond2=" & std_logic'image(Condition2) -- & " cR1=" & integer'image(condR1) -- & " Fcond=" & SLV_to_Hex(Field_cond) -- & " WB_en=" & std_logic'image(WB_en) -- & " GET_en=" & std_logic'image(GET_en) -- & " PUT_en=" & std_logic'image(PUT_en) -- & " A1_en=" & std_logic'image(A1_en) & " PC=" & SLV_to_Hex(PC & '0') & " NPC=" & SLV_to_Hex(NPC & '0') & " RAM_out=" & SLV_to_Hex(RAM_out) & " Result=" & SLV_to_Hex(Result) -- & " DST=" & SLV4_to_Hex(DST) & " R1=" & SLV_to_Hex(R1) & " R2=" & SLV_to_Hex(R2) & " R3=" & SLV_to_Hex(R3) & " R4=" & SLV_to_Hex(R4) & " R5=" & SLV_to_Hex(R5) -- & " SRaddress=" & SLV_to_Hex(SRaddress) -- & " D1=" & SLV_to_Hex(D1) -- & " " & integer'image(safe_to_integer()) ; if PUT_en='1' then report "### PUT=" & integer'image(safe_to_integer(PutWritePort)) & " to register#" & integer'image(safe_to_integer(SRaddress)); end if; if A1_en='1' then j:=safe_to_integer(D1); if Result(6)='1' then case Result(5 downto 0) is when "000001" => report "### ClockPrediv = " & integer'image(j); when "000010" => report "### VitessePrediv = " & integer'image(j); when others => report "### écriture ??????? ["& integer'image(safe_to_integer(Result)) &"] = " & integer'image(j) ; end case; else i:=safe_to_integer(Result(3 downto 0)); case Result(5 downto 4) is when "00" => report "### LUM sur canal " & integer'image(i) & " = " & integer'image(j); when "01" => report "### vitesse sur canal " & integer'image(i) & " = " & integer'image(j); when "10" => report "### DEST sur canal " & integer'image(i) & " = " & integer'image(j); when others => report "### LUM+DESTsur canal " & integer'image(i) & " = " & integer'image(j); end case; end if; end if; end if; end process; GET_data : process(GET_en,SRaddress) variable t:SLVY := (GetReadPort'range=>'0'); begin if GET_en='1' then case SRaddress(3 downto 0) is when "0100" => GetReadPort<=PolyArray(safe_to_integer(NUMERO)); -- POLY when "0101" => GetReadPort<=std_logic_vector(to_unsigned(4, 16)); -- vitesse montée when "0110" => GetReadPort<=std_logic_vector(to_unsigned(20, 16)); -- Vitesse descente when "0111" => GetReadPort<=std_logic_vector(to_unsigned(9000, 16)); -- Luminosité min when others => GetReadPort<=(GetReadPort'range=>'0'); end case; else GetReadPort<=(GetReadPort'range=>'0'); end if; end process; gen_flag: process(clk) begin if rising_edge(clk) then if flag_counter = 0 then flags_in <= '1'; flag_counter <= 7; flag_addr <= std_logic_vector(unsigned(flag_addr)+1); else flags_in <= '0'; flag_counter <= flag_counter-1; end if; end if; end process; bench: process variable i: integer := 0; begin wait for 1 us; clk <= '1'; wait for 1 us; clk <= '0'; wait for 1 us; report " *** releasing reset *** "; reset <= '1'; wait for 1 us; while i < 300000 loop clk <= '1'; wait for 1 us; clk <= '0'; wait for 1 us; i:=i+1; if INV='1' then if (R5="1101111010101101") then -- DEADh ? report "Simulation failed : testbench error at " & SLV_to_Hex(R4) & "h"; else if (R5="0110000000001101") then -- GOOD ? report "Simulation succeeded"; else report "Simulation stopped : Invalid instruction"; end if; end if; wait; end if; end loop; report "### stopping after " & integer'image(i) & " cycles"; wait; end process; end toplevel;