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Instructions structure and forms This form is used by these instructions :
yasep/doc/forms.en.html version 2012-08-11
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The structure of the instructions in the YASEP architecture

The YASEP uses a 16-bits fixed-format instruction word with an optional 16-bits immediate field or a 16-bits extended word. This instruction format is identical for both YASEP16 and YASEP32 : YASEP32 can use 16-bits instructions, YASEP16 can use 32-bit instructions. There is very little difference and the instruction decoder must handle both instruction lengths.

Each instruction can contain :

These fields and flags are not all used at the same time. Some combinations are impossible by construction, some others don't make sense, others can be hidden by the assembler. However, a wide variety of instructions (an opcode followed by register names, immediate data or other flags) can be written by the user. This page explains what are the "instruction forms", how they are designed and when they are used.



An "instruction form" is named after the way it is written in assembly language. It is a sequence of letters that describe each used field :

The YASEP allows only a limited number of forms. The two least significant bits of each instruction determine how to interpret the operands and other fields. The 2 bits create 4 combinations :

The extended form has another flag (aux) so we can also use one of the register fields as a signed 4-bit immediate value (iRR), giving a total of 5 available forms. However, the assembler can make more forms available to the programmer by using certain combinations with unused fields.


Where do the results go ?

The YASEP instructions write the result of an operation (when any) to a register whose address is given by the si4, snd or dst3 fields, depending on the instruction form :

It is a bit unexpected that si4 becomes a destination register field in the long form. It is justified by the fact that snd is the only place in the datapath where operand complementation (the n of snd) can take place.

This system is probably a bit complex and could eventually make architectural development difficult in the far future. However, this is required to keep the instructions compact. Furthermore, in the datapath, what really counts (for performance) is the access time of the operands, not the destination address which can be computed at the same time as the ALU (a good dozen of logic levels). Since pipeline bypass is not considered as an architectural feature, we have more freedom with the fields and can get the most out of each bit, while still keeping the instructions orthogonal. The assembler deals where to put each field for us.


The "short forms"

Let's start with the most simple instruction forms. The short instructions have their LSB cleared and are 16-bit long. This is enough for another flag, a 6-bit opcode and two 4-bit fields.

Note : before 20090730, these two fields were called src1 et src2 and were too confusing... They are renamed si4 and snd since 20090730 to avoid more mistakes.


"Short register form" : Two register addresses

ADD R2, R1 ; R1 <= R1 + R2
1514131211 109876 543210
si4 snd opcode Reg short
R2 R1 ADD 0 0

"Short immediate form" : one immediate and one register address

ADD -3, R1 ; R1 <= R1 + -3
1514131211 109876 543210
si4 snd opcode Imm4 court
-3 R1 ADD 1 0

In practice, these 2 combinations can be used in 5 ways in assembly language, since any of these fields can be more or less useful depending on the kind of operation :

Form "RR" : Register to Register

 ADD R1 R2   ; R2 <- R1+R2
This is the most common form, where si4 and snd are both register operands, and the result goes to snd.


Form "iR" : short immediate to Register

 ADD 2 R3   ; R3 <- 2+R3
Another common form where si4 is used as an immediate value, so snd is used as both source and operand.


Form "Ri" : Register to short immediate

 PUT R1 3   ; Send the contents of R1 to Special Register #3
This is just another way of writing iR when the instruction uses the immediate value as a destination address.


Form "R" : Register

 NEG R1   ; internally : R1 <- 0 - R1
It's also a short way to write that both si4 and si4 fields contain the same register address. The assembler will correctly fill the operand fields if the form is correct for the opcode.


Form "i" : short Immediate

 CRIT 3   ; disable the interrupts during the 3 following instructions
Not used very often but sometimes necessary. si4 is used as an immediate value and snd is ignored.


Form "ALONE" : no operand

 NOP   ; Nop operand needed, all fields ignored.
This is an extreme case where no operand is needed : si4 and snd are ignored.



The "long forms"

YASEP interprets the instruction as 32-bit long when the LSB is set to 1. The 16 lower bits are exactly the same as the short forms. The second LSB selects how to interpret the higher half-word :


"Long immediate form" : Two register addresses and one long immediate value

ADD R2, 1234h, R1 ; R1 <= 1234 + R2
31302928 27262524 23222120 19181716 1514131211 109876 543210
Imm16 si4 snd opcode imm16 long
1234h R2 R1 ADD 0 1

Form "IRR" : long Immediate and Register to Register

 ADD 1234h R2 R1   ; R1 <- 1234h + R2
This is another common form where the operands are snd (a register field) and the 16-bit immediate field. The destination register is given by si4.


Form "IR" : long Immediate to Register

 GET 1234h R1   ; R1 <- SR[1234h]
This form is used for the GET or MOV instructions. snd is ignored because only si4 (the destination address field) makes sense for the operation. The assembler also detects when the immediate address is larger than 4 bits and issues a long or a short form.

This is also used (in conjunction with the ALIAS_IRR flag) by the ROP2 group and the ADD/SUB instructions : this is similar to FORM_iR but with a 16-bit immediate operand. si4 and snd have the same value.

; Both are encoded the same way and perform the same operation :
 OR 1234h R1 R1
 OR 1234h R1

Certain instructions of the YASEP32 can also use the snd field to create a 20-bits immediate value : see the IMM20 flag.
.profile YASEP32 ; the 4 MSB are ignored with YASEP16
 CALL 12345h R1
 MOV 12345h R1

Form "RI" : Register to Immediate

 PUT R1 1234h   ; SR[1234h] <- R1
This form is currently only used for the PUT instruction. It is the same as FORM_IR but the order of the operands is reversed at the assembly language level to obey the rule #1 : "the destination is written at the end of the instruction".



The "extended forms"

The extended forms reuse the short form's structure and add 16 bits for several additional features :

These fields are located so that the other similar fields are 16 bits away. This greatly simplifies the decoding logic and the most important fields (opcode and operands) come first if the instruction bus is only 16 bits wide.

"Extended Register form" : three register addressess

ADD R1, R2, R3 ; R3 <= R1 + R2
31302928 27262524 23222120 19181716 1514131211 109876 543210
dst3 Reg si4 snd opcode Ext long
R3 0 R2 R1 ADD 1 1

Form "RRR" : Register and Register to Register

 ADD R1 R2 R3 ; R3 <- R1+R2
si4 (R1) and snd (R2) are both register operands, and the result goes to dst3 (R3).


"Extended Immediate form" : two register addressess and one 4-bit immediate field

ADD 5, R1, R3 ; R3 <= R1 + 5
31302928 27262524 23222120 19181716 1514131211 109876 543210
dst3 Reg si4 snd opcode Ext long
R3 1 5 R1 ADD 1 1

Form "iRR" : imm4 and Register to Register

 ADD 5 R1 R3 ; R3 <- R1+5
The 4-bit immediate field si4 (5) and snd (R1) are the two operands, and the result goes to dst3 (R3).



Condition codes

The extended instructions contain 7 bits that encode the condition under which the result of the current operation is written back/validated. These bits encode 3 types of predicates :

All the conditions can be negated. The condition "NEVER" is created with inverting the condition "ALWAYS".

The condition codes are designed so the condition "ALWAYS" is represented with all the bits cleared (0).

The "shadow" register is currently undefined. In the first iterations, it will be a copy of the R1 register. Later it can be configured to access I/O pins for example.


To be completed... (conditions, autoupdates...)